1. Field of the Invention
The present invention relates to semiconductor nonvolatile memory and, more particularly, to increase in its memory window and improvement of its ability in holding charges.
2. Description of the Prior Art
Referring to FIG. 1, there is shown an MNOS transistor memory cell. The MNOS (Metal-Nitride-Oxide-Semiconductor) field effect transistor is known to be useful as a memory cell of semiconductor nonvolatile memory, which has the following structure: a gate electrode 21, a silicon nitride layer 19, a silicon dioxide layer 17 and a P type silicon substrate 11 including a N.sup.+ type source 13 and a N.sup.+ type drain 15. The MNOS memory cell can be stored with information by applying electric field to it so that electrons are trapped in the silicon nitride layer 19. To write data into such a cell at a low programming voltage, a method of thinning the silicon nitride layer 19 can be utilized. However, there is a limit to this method because electrons entering the silicon nitride layer 19 are not trapped within the silicon nitride layer 19 because of shortage of trapping distance in this layer 19. This fact limits the thickness of the silicon dioxide layer 17 to 19 nm or more. Accordingly, the programming voltage is limited to 10 Volts.
A memory cell was reported which has new MONOS (Metal-Oxide- Nitride-Oxide-Semiconductor) structure and operates with a programming voltage lower than ever (Suzuki et al., Electronics, 1982, p.107-110).
A memory cell 1 having the above mentioned MONOS-structure is shown in schematic section in FIG. 2. In the figure, within a P type silicon substrate 3, there is provided N.sup.+ type drain 7 and N.sup.+ type source 9, the two regions forming a channel region 32. On top of the channel region 32 there is laminated a silicon dioxide film 5 (2.2 nm thick or so), a silicon nitride film 12 (3.0 nm or so) and a silicon dioxide film 14 (3.3 nm or so) in this order. Further, on top of the film 14 there is formed a polysilicon film 16, which serves as gate electrode. Meanwhile, the construction of the memory cell 1 can be illustrated using an energy band in FIG. 3.
The memory cell 1 constructed as mentioned above has two stable states: one in which a logic "0" has been written therein, that is, electrons are trapped in the silicon nitride film 12, and the other in which a logic "0" has been erased (a logic "1" has been stored), that is, electrons are not trapped in the silicon nitride film 12. The fact that the memory cell 1 can take the two stable states is utilized to fabricate memory.
Operations of writing and erasing information into and from the aforementioned memory cell 1 will be described with reference to the hysteresis loop as shown in FIG. 4. The horizontal axis in FIG. 4 represents gate voltage V.sub.g and the vertical axis threshold voltage V.sub.th. The gate voltage V.sub.g is a voltage applied to the gate electrode 16 of the memory cell. The threshold voltage V.sub.th is a gate voltage at which a current begins to flow between the source and the drain when the voltage applied to the gate electrode is made to increase. In this case, the threshold voltage V.sub.th is given by ##EQU1## where .epsilon. is silicon dielectric constant, N.sub.A is the concentration of impurities within the substrate, V.sub.FB is the flat band voltage, C is the capacity of the gate insulating film, q is the quantity of electron charge dropped in the silicon nitride layer, and .PHI.F is the Fermi level (i.e. the potential energy state of an intrinsic semiconductor with 50% probability of being filled if no forbidden energy band exists).
To write a logic "0" into the memory cell 1, a high voltage which may be as much as some 6 V (Volts) is applied to the gate electrode 16 of the memory cell 1. As a result of this, an electric field that develops between the gate electrode 16 and the channel region 32 causes the electrons within the channel region 32 to have high energy, some of the electrons tunnelling through the silicon dioxide film 5, entering the silicon nitride film 12 and thus trapped therein.
Such a change in charge distribution causes the threshold voltage to increase up to around 1.2 V (see point Q1 in FIG. 4). This means that the memory cell 1 has been made to serve as an enhancement mode transistor having a threshold voltage of approximately 1.2 V. In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see point R1 in FIG. 4).
On the other hand, to erase the logic "0," and store a logic "1", it is necessary to make the trapped electrons return to the channel region 32. This is effected by generating an electric field of the opposite polarity to that produced when writing information by applying a voltage of some 6 V to the channel region 32 relative to the gate electrode 16.
Such a change in charge distribution causes the threshold voltage to change from some 1.2 V to some 0.4 V (see point S1 in FIG. 4). This means that the memory cell 1 has been made to serve as a depletion mode transistor having a threshold voltage of approximately 0.4 V. The state in which the logic "0" is erased is a state in which the memory cell 1 has stored a logic "1." In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see point T1 in FIG. 4).
Further, operations of writing and erasing data into and from the aforementioned memory cell 1 are now described with reference to the energy band view shown in FIG. 3.
In the case where a logic "1" is written into the memory cell 1, electrons charged with high energy due to the applied electric field are made to tunnel through the silicon dioxide film 5 with high potential level, flowing into the silicon nitride film 12. Then the electrons moving in the silicon nitride film 12 mostly trapped near the silicon dioxide film 14. By contrast, in the case where a logic "1" is erased, the trapped electrons are pulled by the electric field in the direction opposite to that in writing data, tunneling through the silicon dioxide film 5 with high potential level, so that they return to the p-type silicon substrate 3.
Referring next to the operation of reading information from the memory cell 1, it is determined whether a logic "0" is stored or a logic "1" is therein, by determining whether or not a current flows through the channel region 32 when a voltage of some 5 V is applied between the source 9 and the drain 7 of the memory cell 1 and a voltage Vs of some 0.8 V is applied to the gate electrode 16. More specifically, when a logic "1" is stored, the threshold voltage of the memory cell 1 a value of appropriately 0.4 V, as shown at point 51 in FIG. 4 However, since the memory cell 1 acted as a depletion mode transistor because of the voltage Vs applied to the gate electrode, the channel regions 32 are conductive. Thus there flows a current through the channel region 32. Meanwhile, when a logic "0" is stored, the threshold voltage of the memory cell 1 is at a positive value of appropriately 1.2 V. Since the memory cell 1 is an enhancement mode transistor where programmed to store a logic "0", even when the voltage Vs applies to the electrode 16, the channel region 32 is non-conductive. Thus there does not flow a current through the channel region 32.
Semiconductor nonvolatile memory (not shown) is constructed by using the memory cells 1 described above and row select transistors (not shown).
However, the conventional memory using the memory cells 1 have the following problems.
In the memory cell 1 with the structure as mentioned above, writing operation is able to be performed at a voltage of some 6 V. But it frequently occurs that the width of the resulting memory window of the memory cell 1 is small. This means the number of electrons trapped in the silicon nitride films 12 is few. The width of the memory window is defined as the difference between the high and low threshold voltages in the hysteresis loop shown in FIG. 4. When the width of the memory window is too small, it is impossible to distinguish between one information thereon (that is, a state where electrons is trapped in the silicon nitride film 12) and the other information (that is, a state where electrons are not trapped in the silicon nitride film 12), so that information may be read out by mistake.
Moreover, long term use of the memory cell 1 tends to decrease the width of memory window. Accordingly, to insure that the memory operates correctly for an adequate lifespan (about 10 years), it is required to prevent reduction in the width of the memory window and maintain the ability to trap and hold charges.
Meanwhile, it is arranged that the silicon dioxide film 5 is so thin that information thereon can be written into the memory cell at a low voltage of some 6 V. This is why trapped electrons in writing operation can return the channel region 32. In other word, the memory cell has disadvantages in its ability of holding charges so that information may be read out by mistake.